1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and more particularly to a semiconductor device manufacturing method with respect to the light exposure of chip patterns on each semiconductor wafer in a lithography process.
2. Description of Related Art
In the lithography process among the manufacturing processes of semiconductor devices (chips), a reduction projection aligner (stepper) is often used to carry out light exposure for chip patterns formed on a reticle (mask) repetitively onto the photoresist on the subject semiconductor wafer. The reticle has a plurality of rectangular chip patterns formed to cut the wafer into a plurality of chips and the photoresist is patterned into one shot of chips. Those chip patterns are disposed so that the maximum number of semiconductor devices can be obtained from each semiconductor wafer by taking consideration to the reduction of the chip manufacturing cost. There are some techniques having been proposed for such disposition of chip patterns, which are disclosed in the following patent documents.
For example, the patent document 1 discloses a method that determines how to dispose chip patterns entirely in an element forming effective region. According to the method, in the unit element formation effective region, a plurality of parallel lines are disposed at intervals of the second line length of the region, thereby forming a plurality of parallel line segment regions and each of those segment regions is disposed independently from other parallel line segment regions so that the maximum number of unit element forming regions can be obtained in each of the parallel line segment regions. The disposition of such a unit element forming region in each parallel line segment region is determined as that in the whole element formation effective region.
On the other hand, the patent document 2 discloses a method that forms die regions on each object semiconductor wafer. According to the method, at first, a first set of parallel scribe lines is formed. Those scribe lines are separated actually from each other at equal intervals and extended in the direction of the chord by crossing the semiconductor wafer. Then, a second set of parallel scribe lines is formed so as to be separated from each other and extended in the direction of the chord by crossing the semiconductor wafer. A third set of parallel scribe lines are formed so as to be separated actually from each other at equal intervals and extended in the direction of the chord by crossing the semiconductor wafer. The third set of scribe lines crosses the first set of scribe lines at a second minus angle “θ” that is different from the first angle at each point where the first and second sets of scribe lines cross each other. This method defines a plurality of die regions enclosed by those first to third sets of scribe lines on the object semiconductor wafer.
Furthermore, the third patent document discloses a shot map creating method that defines disposition of a plurality of shot regions for forming chip patterns on a substrate by drawing a mask pattern formed on a reticle. According to the method, a plurality of chip patterns for cutting out a plurality of chips are formed in the plurality of shot regions respectively, then the plurality of shot regions are disposed so that the maximum number of chips can be positioned in the effective light exposure region on the substrate, that is, in the effective substrate region.    [Patent document 1] Japanese Patent Application Laid Open No. 2006-41005    [Patent document 2] Japanese Patent Application Laid Open No. Hei 6 (1994)-97279    [Patent document 3] Japanese Patent Application Laid Open No. 2001-230181